1. Field of the Invention
The present invention relates to high speed digital circuits, and in particular, to high speed time-division demultiplexor circuits.
2. Description of the Related Art
Modern data networks in which multiple computers are interconnected for sharing instructions and data, e.g., local area networks ("LANs"), typically operate over a serial data medium. The computers themselves, however, typically process their instructions or data internally in parallel formats. Therefore, to interface to the data network, each computer must use a 1:M demultiplexor to receive data or instructions from the network, where M is the number of parallel bits of instructions or data which must be time-division demultiplexed from a serial bit stream.
As shown in FIG. 1, a 1:M demultiplexor has a serial data input D, a clock input CLK for clocking the serial data input D into the demultiplexor, M parallel data outputs Q.sub.0 -Q.sub.M-1, and a trigger output T. The clock input signal CLK must have a frequency equal to the bit rate of the serial input signal D. The trigger output T has a frequency equal to that of the clock input signal CLK (i.e., the bit rate of the serial input D) divided by the number M of parallel data output bits. Thus, the clock input signal CLK must have a frequency equal to M times the bit rate of the M parallel data outputs Q.sub.0 -Q.sub.M-1.
FIG. 2 illustrates, for the case of M=4 bits, a simple type of time-division demultiplexor based upon an M-bit shift register. The input data D is serially loaded, i.e., shifted in, and on every fourth clock pulse the data is transferred to the output latches. The clock signal CLK, used to clock the D-type flip-flops in the shift register, is also frequency-divided to produce the clock signals for the output flip-flops and the trigger output T.
With a shift register based, time-division demultiplexor as shown in FIG. 2, it will be appreciated that the architectures for the shift register section, the output latches and the frequency divider require the following: EQU T.sub.bit &gt;T.sub.CLK.fwdarw.Q
where ##EQU1##
Thus, the maximum bit rate for the demultiplexor architecture of FIG. 2 is determined in accordance with the following: ##EQU2##
In practice, however, the shift register based, time-division demultiplexor of FIG. 2 cannot achieve this theoretical maximum speed due to the effects of signal delay variations among the various signal paths for the input and output signals. Furthermore, the demultiplexor of FIG. 2 must be operated with a clock signal CLK frequency equal to the incoming serial bit rate. This can be a problem when this type of demultiplexor is used to interface with a very high speed data network medium, such as an optical fiber. Full advantage of the extremely high bit rate capabilities of an optical fiber cannot be realized by simply clocking a solid state electronic demultiplexor at a higher rate. In other words, the electronics simply cannot reliably keep pace with the elevated bit rates possible with optical fibers.
In an attempt to increase the architecturally limited maximum bit rate of the demultiplexor of FIG. 2, and to overcome the requirement of using a clock signal CLK having a frequency equal to the incoming serial bit rate, the interleaved, time-division demultiplexor of FIG. 3 was developed. (As in FIG. 2, the illustrated demultiplexor in FIG. 3 is for the case of M=4 bits.) The serial input data D is loaded sequentially into input D-type flip-flops and then transferred as the parallel data outputs Q.sub.0 -Q.sub.3 via output D-type flip-flops (for Q.sub.0 -Q.sub.2) or directly (for Q.sub.3). The input flip-flops are clocked with various phases of the frequency-divided, multiphase clock signal, and the output flip-flops are clocked with the same phase of the multiphase clock signal which forms the trigger T output.
The input clock signal CLK/2 for the interleaved demultiplexor of FIG. 3 has a frequency which is half that of the clock signal CLK for the demultiplexor of FIG. 2. It is further frequency-divided with multiple phases by coupling two D-type flip-flops together as a divide-by-two frequency divider circuit.
For the demultiplexor of FIG. 3, it will be appreciated that the input data flip-flops, in conjunction with the clock frequency divider flip-flops, require the following: EQU T.sub.bit &gt;T.sub.CLK.fwdarw.Q /2
Therefore: ##EQU3##
Within the demultiplexing input stage, each flip-flop requires only that data be valid at its output within one bit period T.sub.bit. This in theory requires the following: EQU T.sub.bit &gt;T.sub.D,1,2.fwdarw.Q
where: T.sub.D1,2.fwdarw.Q .apprxeq.T.sub.min
Therefore: ##EQU4##
Hence, the interleaved time-division demultiplexor of FIG. 3 appears to be faster than the shift register based, time-division demultiplexor of FIG. 2 by a factor of two. However, the interleaved demultiplexor of FIG. 3 with single phase output latches has practical limitations. The use of single stage, single phase output latches requires that each input data bit be latched through its input latch stage within one bit period T.sub.bit after the triggering edge of the 180.degree. phase clock signal so that all demultiplexed bits Q.sub.0 -Q.sub.3 can be latched for outputting by the 270.degree. phase clock signal. In other words, this requires the following: EQU T.sub.bit &gt;T.sub.CLK.fwdarw.Q
Thus, since the overall maximum bit rate cannot exceed the maximum bit rate of the slowest portion of the circuit, the maximum bit rate for the interleaved demultiplexor of FIG. 3 is the following: ##EQU5##
Thus, the interleaved time-division demultiplexor of FIG. 3 is no faster in theory than the shift register based, time-division demultiplexor of FIG. 2.
Hence, it would be desirable to have a 1:M time-division demultiplexor with an architecture providing a higher maximum bit rate while still requiring a clock signal having a frequency lower than the incoming serial bit rate.